VDMOS器件终端结构设计及优化

Design and Optimization of VDMOS Device

击穿电压是VDMOS器件的重要参数之一,器件的耐压能力主要由终端结构的击穿电压决定,但结曲面效应和表面电荷的存在制约着击穿电压的提高。设计的这款400V VDMOS的场限环终端结构,改善了结曲面效应,但表面电场较大,在此基础上,充分利用场板降低表面电场的作用,结合场限环构成场板-场限环终端结构,减少了场限环的数量,节省了16.67%的终端宽度,实现了440.6V的击穿电压。此外,没有增加额外的掩膜或工艺步骤,工艺兼容性好,易于实现。

Breakdown voltage,as one of important parameters of VDMOS device,is limited by the termination of VDMOS device. However,high electric field intensity at the edges of the junction due to junction curvature and surface charges has important effect on breakdown of VDMOS device. In this paper,a 400 V VDMOS with field limiting ring（ FLR） termination is designed to improve high electric field intensity at the edges of the junction due to junction curvature. But surface electric field is high,based on the above design of VDMOS termination,field plate（ FP） is associated with field limiting ring to form an FP- FLR combination structure. This terminal structure not only lowers the surface electric field,but reduces the number of field limiting ring. The result shows that the breakdown voltage of VDMOS is 440. 6V,and the length of termination is decreased by 16. 67%. Besides,without any additional masks and process flows,this termination can be more simply implemented and has good compatibility.