基于FPGA的E1时钟恢复方案的设计和实现

Design and implement of E1 Clock recovering scheme based on FPGA

提出了一种利用FPGA来实现的E1时钟恢复方案。根据E1数据帧的特点,设计了FPGA内部的数字锁相环。通过对传统数字锁相环的鉴相器进行改进,设计基于FIFO的积分型采样鉴相器。进行了误码测试和输入口允许频偏测试,测试结果表明恢复出的E1信号满足相关标准要求。

This paper presents a kind of E1 clock recovery scheme based on FPGA. It designs the digital phase-locked loop within FPGA according to the characteristics of the E1 data frame. Moreover, it improves the traditional phase detector and designs the integral sampling phase detector based on FIFO. It performs the BER test and input interface frequency offset test, test results reveal the recovered E1 signal reaches relevant standards.