基于FPGA的E1成帧器的设计与实现

Design and Implementation of E1 Into Frame Based on the FPGA

提出一种基于FPGA的E1成帧器的设计与实现,分析E1基本帧和复帧的结构,设计基于FPGA的E1基本帧、复帧的接收同步检测和发送形成帧的电路,完成E1成帧器的RTL描述,并利用Model Sim仿真软件对设计的电路进行仿真验证。

Proposes the design and implementation of a kind of E1 into frame Based on FPGA, analyzes the basic frame and E1 frame structure, basic frame, designs E1 multi-frame receiving synchronous detection and sending form the frame of the circuit based on FPGA, completes the E1 frame becoming of RTL description, and uses Model Sim simulation software to design the circuit simulation.