MIMO-OFDM系统中低功耗FFT/IFFT处理器设计

Design of Low Power Consumption FFT / IFFT Processor in MIMO-OFDM System

针对IEEE 802.11ac多输入多输出(MIMO)正交频分复用(OFDM)系统,设计一种支持8组128点数据并行处理的低功耗FFT/IFFT处理器,利用RAM实现对输入和输出数据的顺序调整,使得处理器可以与MIMO-OFDM系统中其他模块直接进行数据通信。该处理器通过Verilog语言实现,采用TSMC 65 nm工艺库进行逻辑综合,结果表明其在0.9 V,125℃的工艺库最差工作条件下可达到100 MHz工作频率,与利用寄存器延时单元实现输入和输出数据顺序调整的FFT/IFFT处理器相比,总的门数减少了32.98%,功耗降低了79.4%。

This paper proposes a low power consumption FFT/IFFT processor for IEEE 802.1 lac Multiple Input Multiple Output-Orthogonal Frequency Division Multiplexing （MIMO-OFDM） system. The processor can support the parallel processing of eight spatial data groups, and each group has 128 points. The RAM data reorder architecture is used to realize eight input and output spatial data groups in natural order, thus the processor can be used directly to communicate with other modules in the MIMO-OFDM system. The proposed FFT/IFFT processor is designed in Verilog and synthesized using TSMC 65 nm process library. The operating frequency is up to 100 MHz under 0.9 V and 125 ~（7, the worst operating condition of the process library. Compared with the FFT/IFFT processor which uses register delay elements to adjust the order of input and output data, the proposed FFT/IFFT processor can realize 32.98% reduction in the gate count and 79.4% reduction in power consumption.