期刊文献+

参数分簇层次化片上网络拓扑结构 被引量:2

Parameter and Cluster Based Hierarchical Mesh Structure for Network-on-Chip
下载PDF
导出
摘要 多核系统集成度不断增加,造成片上网络的延迟和吞吐性能迅速下降。提出基于参数分簇的层次化片上网络结构,设计3类基本分簇作为单元模块,搭建不同节点规模下的层次化结构。实验结果表明,在局部化流量模式下,文中结构比传统Mesh和Clustered Hierarchical Mesh在256节点时的延迟分别降低18.76%和17.31%,吞吐提升18.57%和12.97%,资源仅增加25%和10%。 With the increasing size of chip-multi-processor (CMP) , the latency and throughput per- formance of conventional NoC is getting worse. This paper proposes a new parameter-based hierar- chical mesh NoC (PHNoC). Three base-clusters are designed to form multi-layers and three param- eters are presented to design different size of CMP. Experimental results demonstrate that, compared with Mesh and CHMesh, PHNoC reduces latency by 18.76% and 17.31% and improves throughput by 18.57% and 12.97% , with only 25% and 10% more resources overhead respectively under size of 256 and localized traffic.
出处 《信息工程大学学报》 2016年第3期346-352,共7页 Journal of Information Engineering University
基金 河南省自然科学基金资助项目(122300413201)
关键词 片上网络 层次化互连 分簇结构 参数化设计 network-on-chip hierarchical interconnection clustered structure parameterized design
  • 相关文献

参考文献12

  • 1Kim J, Choi K, Loh G. Exploiting new Interconnect technologies in on-chip communication [ J ]. Emerging and Selected Topics in Circuits and Systems, 2012, 2 (2) : 124-136.
  • 2Winter M, Prusseit S, Gerhard P F. Hierarchical routing architectures in clustered 2D-mesh networks-on-chip [ C ]// ISOCC2010. 2010:388-391.
  • 3Wanas M A, Abd E1 Ghany M A, Hofmann K. HybridMesh-Ring wireless NoC for multi-core system [ C ]// DDECS2013. 2013: 295-296.
  • 4Puttmann C, Niemann J C, Porrmann M, et al. Giganoc- a hierarchical network-on-chip for scalable chip-multipro- cessors [ C ]//Euromicro Conference on Digital System Design Architectures, Methods and Tools, 2007. 2007: 495 -502.
  • 5Lee S, Togawa N, Sekihara Y, et al. A hybrid NoC ar- chitecture utilizing packet transmission priority control method[ C ]//APCCAS 2012. 2012:404-407.
  • 6Balfour J, Dally W J. Design tradeoffs for tiled CMP on- chip networks[ C ]// Proc. Annual International Confer- ence on Supercomputing. 2006: 187-198.
  • 7孔峰,韩国栋,沈剑良,简刚.一种基于Mesh结构的新型层次化片上网络拓扑结构[J].电子与信息学报,2014,36(10):2536-2540. 被引量:7
  • 8Qian z, Bogdan P, Tsui C Y, et al. Performance evalua- tion of multicore systems : From traffic analysis to latency predictions (Embedded tutorial)[ C ]// ICCAD 2013. 2013 : 82-84.
  • 9Heirman W, Dambre J, Stroobandt D, et al. Rent rule and parallel programs: characterizing network traffic be- havior[ C ]//Proceedings of the 2008 international work- shop on System level interconnect prediction. 2008: 87-94.
  • 10KahngA B, Li B, Peh LS, etal. ORION 2.0: afast and accurate NoC power and area model for early-stage design space exploration [ C ]//Proceedings of the con- ference on Design, Automation and Test in Europe. Eu- ropean Design and Automation Association. 2009: 423 -428.

二级参考文献16

  • 1朱晓静,胡伟武,马可,章隆兵.Xmesh:一个mesh-like片上网络拓扑结构[J].软件学报,2007,18(9):2194-2204. 被引量:17
  • 2Xiang D and Zhang Y. Cost-effective power-aware core testing in NoCs based on a new unicast-based multicast scheme[J] IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2011, 30(1): 135-147.
  • 3Marculescu R, Ogras U Y, Shiuan P L, et al.. Outstanding research problem in NoC design: system, micro-architecture, and circuit perspectives[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuit and System, 2009, 28(1): 3-21.
  • 4Taylor M B, Lee W, Miller J, et al.. Evaluation of the raw microprocessor: an exposed-wire-delay architecture for ILP and streams[C]. Proceedings of the 31st Annual International Symposium on Computer Architecture, Munich, 2004: 2-13.
  • 5Feero B and Pande P. Performance eMuation for three-dimensionM networks-on-chip[C]. IEEE Computer Society Annum Symposium on VLSI, Porto Alegre, 2007: 305-310.
  • 6Chiu Ge-ming. The odd-even turn model for adaptive routing[J]. IEEE Transactions on Parallel and Distributed Systems, 2000, 11(7): 729-738.
  • 7Balfour J and Dally W J. Design trm:leoffs for tiled CMP on-chip networks[C]. 20th Annual International Conference on Supercomputing, New York, 2006: 187-198.
  • 8Samia Loucif. Performance evaluation of hierarchical-torus NoC[C]. 27th International Conference on AdvancedInformation Networking and Applications Workshops, Barcelona, 2013: 837-842.
  • 9Kim J, Balfour J, and Dally W. Flattened butterfly topology for on-chip networks[C]. Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture, Chicago, 2007: 172-182.
  • 10Penaranda R, Gomez C, et al.. A new family of hybrid topologies for large-scale interconnection networks[C], llth IEEE International Symposimn on Network Computing and Applications, Cambridge, MA, 2012: 220-227.

共引文献6

同被引文献15

引证文献2

二级引证文献3

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部