一种自偏置锁相环电路的分析与测试

Analysis and measurement of a self-offset Phase-Locked Loop

自偏置锁相环电路结构自提出以来便受到了极大的关注,人们普遍认为其可以改善锁相环的相位噪声。为了验证这种结构能否改善传统锁相环电路的相位噪声性能,根据锁相环的基本理论设计并实现了一种可进行重新配置的锁相环电路结构,电路中的锁相环结构可以在传统锁相环、自偏置锁相环和普通偏置锁相环之间进行切换。使用信号源分析仪分别测试得到了这3种结构的相位噪声性能:自偏置锁相环的带内相位噪声比普通锁相环恶化了约6 d B,而采用普通偏置锁相环使环路等效分频比减小5的相位噪声比普通锁相环改善了约14 d B。理论与测试结果均表明,自偏置锁相环和普通锁相环相比,环路反馈回路中的分频比并没有有效降低,因此自偏置锁相环的相位噪声性能并没有得到改善。

The self-offset Phase-Locked-Loop（PLL） structure, which is considered to have the ability to improve the phase noise performance of the PLL, has gained much attention. In order to verify this viewpoint, a reconfigurable circuit board is designed and implemented based on the basic theory of the PLL. The phase-locked loop structure can be switched among the conventional, self-offset and offset topologies, whose phase noise performances are measured by Agilent signal source analyzer, respectively. The in-band phase noise performance of the conventional PLL is better than that of the self-offset one by 6dB, and the phase noise performance of the offset PLL is improved about 14dB compared to the conventional one. The experimental results indicate that the frequency dividing-ratio in the feedback path of the loop has not been reduced in self-offset PLL compared to conventional PLL, thus the phase noise performance has not been improved.