摘要
对大功率LED封装器件进行了封装界面层裂的热仿真分析,在芯片粘结(DA)层上构建了不同的界面层裂模型,探究了不同层裂形状、位置及分布时界面层裂对芯片热传递的影响规律。结果表明:随着界面层裂面积的增加,LED芯片结温以14℃/mm^2以上的速率增大,层裂面积达到36%时,芯片最高温度为68.68℃,相比无层裂时升高了9.8%;并且界面层裂处于DA层的下界面比上界面对芯片温度分布影响更大;此外,针对同一界面的层裂缺陷,相对于边缘位置和中心位置,封装边角位置的层裂对整体LED封装热传输能力的阻碍作用更明显。
Thermal simulation analysis of interface delamination of high power LED package device was carried out. Different interface delamination models were constructed on die attach layer, and influences of the different shapes, positions and distributions of delamination on heat transfer of the chip were explored. The results show that with the increase of interface delamination area, the junction temperature in LED chip increases with the rate of more than 14 ℃ /mm2. When the delamination area is 36%, the maximum temperature of the chip is 68.68 ℃, which is 9.8% higher than that of the non-delamination interface. In addition, temperature distribution of the chip whose delamination occurs at the underside (die attach-to-metal substrate interface) of the die attach layer is larger than that of the upside (chip-to-die attach interface). For the same interface, that delamination occurs at edge angle position is more harmful for blocking heat transfer in the overall LED package than that at the edge position and the center position.
出处
《电子元件与材料》
CAS
CSCD
2016年第8期76-80,共5页
Electronic Components And Materials
基金
国家自然科学基金资助(No.51366003)
广西研究生教育创新计划资助(No.YCBZ2015037)
广西中青年教师基础能力提升项目资助(No.KY2016YB148)
关键词
大功率LED
芯片粘结层
界面层裂
有限元分析
热仿真
传热性能
high power LED
die attach layer
interface delamination
finite element analysis
thermal simulation
heat transfer performance