基于FPGA的多节点1553B总线协议处理器的实现

Implement of multi-core 1553B protocol processor based on FPGA

研究设计了一种多节点的1553B总线协议处理器,可以模拟整套1553B总线系统,既可以作为测试设备,也可作为总线上的多个节点在实际应用中使用。针对总线协议处理器逻辑与存储资源占用高、难以单片实现的问题,提出了多核MIMD架构的实现思路,有效地降低了逻辑资源的使用量,使其可以在单片FPGA上实现。基于软硬件融合的理念,通过自定义专用指令集增加指令并行度来提高指令执行的效率,增强了系统的实时性,使其可以在低频时钟下运行,从而降低了系统的功耗。

A multi-node 1553B bus protocol processor is implemented which can simulate a whole 1553B bus system as a test device or be nodes on bus in application simultaneously. To reduce the utilizing of logic source, a multi-core MIMD architecture is proposed so that implement is possible on single chip. Adopted the idea of combination of HW and SW, a specialized instruction set is defined to improve efficiency. This al- lows the system working at low frequency so power is reduced.