摘要
A scalable readout system （SRS） is designed to provide a general solution for different micro-pattern gas detectors in various applications. The system mainly consists of three kinds of modules： the ASIC card, the adapter card and the front-end card （FEC）. The ASIC cards, mounted with particular ASIC chips, are designed for receiving detector signals. The adapter card is in charge of digitizing the output signals from several ASIC cards. The FEC, edged-mounted with the adapter, has field-programmable gate array （FPGA）-based reconfigurable logic and I/O interfaces, allowing users to choose different ASIC cards and adapters for different experiments, which expands the system to various applications. The FEC transfers data through Gigabit Ethernet protocol realized by a TCP processor （SiTCP） IP core in FPGA. By assembling a flexible number of FECs in parallel through Gigabit Ethernet, the readout system can be tailored to specific sizes to adapt to the experiment scales and readout requirements. In this paper, two kinds of multi-channel ASIC chip, VA140 and AGET, are applied to verify the scalability of this SRS architecture. Based on this VA140 or AGET SRS, one FEC covers 8 ASIC （VA140） cards handling 512 detector channels, or 4 ASIC （AGET） cards handling 256 detector channels, respectively. More FECs can be assembled in crates to handle thousands of detector channels.
A scalable readout system （SRS） is designed to provide a general solution for different micro-pattern gas detectors in various applications. The system mainly consists of three kinds of modules： the ASIC card, the adapter card and the front-end card （FEC）. The ASIC cards, mounted with particular ASIC chips, are designed for receiving detector signals. The adapter card is in charge of digitizing the output signals from several ASIC cards. The FEC, edged-mounted with the adapter, has field-programmable gate array （FPGA）-based reconfigurable logic and I/O interfaces, allowing users to choose different ASIC cards and adapters for different experiments, which expands the system to various applications. The FEC transfers data through Gigabit Ethernet protocol realized by a TCP processor （SiTCP） IP core in FPGA. By assembling a flexible number of FECs in parallel through Gigabit Ethernet, the readout system can be tailored to specific sizes to adapt to the experiment scales and readout requirements. In this paper, two kinds of multi-channel ASIC chip, VA140 and AGET, are applied to verify the scalability of this SRS architecture. Based on this VA140 or AGET SRS, one FEC covers 8 ASIC （VA140） cards handling 512 detector channels, or 4 ASIC （AGET） cards handling 256 detector channels, respectively. More FECs can be assembled in crates to handle thousands of detector channels.
基金
Supported by National Natural Science Foundation of China(11222552)
