摘要
提出了一种基于传输门逻辑的低能耗三输入AND/XOR门设计电路.基于55nm CMOS工艺,采用HSPICE仿真软件在不同工艺角下对门电路进行后仿真分析,并与已有的AND/XOR门电路进行对比.仿真结果表明该电路的性能良好,在典型工艺角下,提出的电路的功耗、速度和功耗-延时积的改进量最高分别可达10.08%,29.03%与36.12%,满足低能耗的设计要求.
A transmission gate logic based low energy consumption 3-input AND/XOR gate is proposed. Under 55 mn CMOS process, the post-simulations of the circuit under different process comers are carried out by using HSPICE and compared with the published circuits. The simulation results show that the performance of this circuit is good, under typical process corner, the improvement of the proposed circuit can be up to 10. 08%, 29.03% and 36. 12% respectively in terms of the power, delay and power delay product, which meets the design requirement of low energy.
出处
《微电子学与计算机》
CSCD
北大核心
2016年第8期102-106,共5页
Microelectronics & Computer
基金
国家自然科学基金重点项目(61131001)
关键词
与/异或
功耗
功耗一延时积
低能耗
AND/XOR
power
power delay product
low energy consumption
