Verifier提高验证完备性

Verifier-Improve the simulation verification completeness

随着集成电路设计技术的不断发展,电路设计中经常出现一些问题。因此,设计验证技术成为了电路设计中不可或缺的部分。如何提高验证完备性,是验证技术的难题之一。本文介绍了Cadence最新发布的适用于模拟设计的ADE Verifier的工具使用流程,以及根据海思业务需求定制的使用方法。该工具整合了验证工具ADE Explorer和ADE Assembler的特性,完善了模拟电路设计验证流程,解决了模拟设计验证完备性中的问题。

With the technology of the integrated circuit design developing, some problems in the circuit design also arise. The veri-fication technology plays an important role in the circuit design. At present, it is urgent for us find solutions of improving the veri-fication completeness. This paper describes a tool newly published by Cadence, that is, ADE Verifier. In this paper, you will get to know the usage of ADE Verifier and acquire its customized application in Hi Silicon. By integrating the identities of both ADE Explorer and ADE Assemble, meanwhile, and by improving the process in a simulation verification, ADE Verifier has been fairly helpful to solve the completeness problem effectively.