高速SRAM编译器时序算法

High-Speed SRAM Compiler Timing Algorithm

介绍了一种通用嵌入式存储器(SRAM)编译器时序建模的方法。通过对存储器关键路径延时分析,时序模型采用分段拓展的建模方式,用Rows、Columns来对SRAM进行分段,分别讨论各段对时序的影响。采用双线性插值法对模型进一步优化,较大程度上提高了模型的精度。最后与ARM公司0.13μm工艺的存储编译器进行了验证和对比。结果表明,该模型能够较为精确地描述存储编译器时序。

The paper introduces a method of SRAM compiler timing modelling. By analyzing the delay of the critical path, timing model adopts segmented expansion method to discuss the impact of segments on timing. The bilinear interpolation method further optimizes the timing model, thereby greatly improving the accuracy. The compiler is then compared with the ARM 0.13μm memory compiler. The results show that the model is capable of accurate description of the timing.