基于FPGA的SAR数据源时序测试设计与实现

Design and Implementation of Testing Time Sequence inSAR Load Simulator based on FPGA

针对星载合成孔径雷达（SAR）中数传分系统接收数据时序测试需求,设计一种基于FPGA的SAR数据源系统,该系统以XC5VLX330T为核心构建数据处理单元,完成SAR仿真数据存储、钟码关系合成以及BIT等功能,并设计通讯单元与输出接口单元完成人机交互与LVDS数据发送.同时,针对数传分系统钟码关系拉偏测试需求,提出一种基于FPGA原语的延时单元设计方法,该延迟单元采用IODELAY原语,通过时序约束实现正反向时钟拉偏功能.仿真与试验结果表明,SAR数据源具备时序拉偏测试功能,钟码关系调整范围可达-8m至8m,步进1m,系统运行稳定,满足设计要求.

In spaceborne synthetic aperture radar （SAR）, in allusion to the requirement of testing timesequence in data transmission subsystem, a new design of SAR load simulator system is implemented,which is based on FPGA. The system adopts XC5VLX330T as basic to build data processing unit, whichis used to implement mass SAR simulation data storage, sequence synthesis of clock -data and BITfunction. The man-machine and LVDS output interface are also implemented by communication unitand LVDS output unit. To meet the requirements of timing perturbation injection in data transmissionsubsystem test, the delay unit based on IODELAY primitive, is designed by timing rules. Finally, theperformance and robustness are assessed through the simulation and test, and the results show that therange of timing perturbation is from -8ns to 8 ns with 1ns step, when delay unit is working in SAR loadsimulator system.