ARINC659总线接口的命令表加速器研究与设计

Research and design for command table accelerator of ARINC659 bus interface

ARINC 659底板总线是一种具有总线传输时间确定性和半双工传输特性的线性多点串行数据总线,它采用表驱动协议(TDP),无总线冲突和访问时延,具有高可靠性、高冗余度、高容错性等特点。文中首先提出ARINC659总线接口的系统框架,重点针对659总线接口内部的命令表加速器这一关键部件进行了研究设计,提出了一种专用流水线的设计方法,并最终通过仿真验证。

ARINC659 is a linear,multi-drop,serial data bus,which has the characteristics of bus transmission time certainty and half duplex transmission. Driven by command table,ARINC659 bus has no bus conflict and access delay. ARINC659 bus is a highly reliabe backplane data bus which has the features of high fault tolerance,high redundancy. From the beginning of this paper,it puts forward the system framework of ARINC659 bus interface,then analyzes and implements command table accelerator which is a key component in ARINC659 bus interface,and addresses one kind of pipeline methodology which is used in the accelerator design. Finally,the HDL simulation and verification is passed under virtual enviroment.