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集成I/O硬件压缩加速器的Hadoop系统结构

Integrated I/O hardware compression accelerators of Hadoop system architecture
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摘要 随着大数据的发展,Hadoop系统成为了大数据处理中的重要工具之一。在实际应用中,Hadoop的I/O操作制约系统性能的提升。通常Hadoop系统通过软件压缩数据来减少I/O操作,但是软件压缩速度较慢,因此使用硬件压缩加速器来替换软件压缩。Hadoop运行在Java虚拟机上,无法直接调用底层I/O硬件压缩加速器。通过实现Hadoop压缩器/解压缩器类和设计C++动态链接库来解决从Hadoop系统中获得压缩数据和将数据流向I/O硬件压缩加速器两个关键技术,从而将I/O硬件压缩加速器集成到Hadoop系统框架。实验结果表明,I/O硬件压缩加速器的每赫兹压缩速度为15.9Byte/s/Hz,集成I/O硬件压缩加速器提升Hadoop系统性能2倍。 With the development of big data, Hadoop systems become an important tool, but I/O operations impede their performance improvement in practical applications. Hadoop usually decreases its' I/O operations by using software to compress data. However, data compression by software is slower than hardware accelerators. When Hadoop runs on Java virtual machines, it cannot directly call I/O hardware accelerators. To avoid getting data from the Hadoop system and transferring the data to I/O hardware accelerators, a compressor and decompressor class of Hadoop and a C++ dynamic linking library are employed in the Hadoop system. Experimental results show that both techniques can integrate I/O hardware accelerators into the Hadoop system frame work, the efficiency of I/O hardware compressor is 15.9Byte/s/Hz, and the performance of the Hadoop system can be improved by two times.
出处 《计算机工程与科学》 CSCD 北大核心 2016年第8期1524-1529,共6页 Computer Engineering & Science
基金 华为技术有限公司资助项目(YB2014100047)
关键词 HADOOP I/O 硬件压缩加速器 Hadoop I/O hardware compression accelerator
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参考文献13

  • 1Hadoop [EB/OL]. [2015-05-16]. http://hadoop.apache.org.
  • 2MapReduce [EB/OL]. [2015-05-16]. http://mareduce.apache.org.
  • 3Ganglia[EB/OL].[2015-05-16].http://ganglia.info/.
  • 4TeraSort[EB/OL]. [2015-05-16]. http://www.highlyscalablesystems.com/3235/hadoopterasortbenchmark.
  • 5Salomon D.Data compression: The complete reference[M].New York:Springer Science & Business Media,2000.
  • 6Putnam A,Caulfield A M,Chung E S,et al.A reconfigurable fabric for accelerating largescale datacenter services[J].IEEE Micro,2015,35(3): 10- 22.
  • 7Shan Y,Wang B,Yan J,et al.FPMR: MapReduce framework on FPGA[C]∥Proc of the 18th Annual ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA’10),2010:93-102.
  • 8Freund Y,Iyer R,Schapire R E,et al.An efficient boosting algorithm for combining preferences[J].Journal of Machine Learning Research,2003(4):933- 969.
  • 9Tsoi K H,Luk W.Axel: A heterogeneous cluster with FPGAs and GPUs[C]∥Proc of the 18th Annual ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA’10),2010:115-124.
  • 10Andrew M,Damir J,Kanak A.FPGAbased application acceleration: Case study with gzip compression/decompression streaming engine[C]∥Proc of International Conference on ComputerAided Design (ICCAD’13),2013:1.

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