一种面向三维众核微处理器的新型NoC拓扑结构

A novel NoC topology for 3D many-core microprocessors

三维微处理器具有集成度高、全局互连线短及连接部件多的优势,但是传统的三维拓扑结构在大规模系统中无法充分利用垂直方向上低延时高带宽的特性,很难满足大规模众核微处理器低直径、高带宽、高扩展性的需求。针对三维NoC网络直径大、可扩展性要求高以及路由端口多的问题,提出了一种基于多级垂直域的三维拓扑结构—V-Spidergon,其在水平层上采用Spidergon结构,在垂直方向上采用多级垂直域扩展结构,域内及域间均实现全互连。实验数据表明,在8层、16层和32层堆叠下,V-Spidergon结构的延时较3D-Mesh分别降低15.1%、28.5%和55.7%,较NoC-Bus分别降低11.5%、32.7%和77.6%;在15%和100%负载率注入情形下,V-Spidergon的平均延时表现出与水平层数增加不相关的特性。

3D microprocessors have advantages of highqevel integration, short global interconnection and more connecting parts. However the traditional 3D topology cannot take full advantage of the characteristics of 3D integrated circuits in the vertical direction. It is difficult for these structures to meet the requirements of large-scale many-core processors, such as short diameter, high-bandwidth and highly scalability. We propose a 3D on-chip interconnection network topology, called V-Spidergon. In the hori- zontal layer, the V-Spidergon adopts the Spidergon topology in the horizontal layer and a domain-based interconnected structure in the vertically direction. The entire vertical network is divided into multi-level domains according to the hierarchical domain thought, and every domain interconnects with each other. Simulation results show that the time delays in 8 layers, 16 layers and 32 layers of the V-Spidergon are lower than those of the 3D-Mesh by 15.1%, 28.5%, 55.7% respectively, and are also lower than those of the NoC Bus by 11. 5% 32. 7% and 77. 6% respectively; under injections of 15% and 100% load rates, the average time delay of the V-Spidergon does not increase with the growth of horizontal layers.