65nm工艺下单粒子加固锁存器设计

Single Event Hardening Latch Design in 65 nm Technology

随着工艺尺寸的缩减,单粒子引发的软错误成为威胁电路可靠性的重要原因.基于SMIC 65 nm CMOS工艺,提出一种单粒子加固锁存器设计.首先针对单粒子翻转,使用具有状态保持功能的C单元,并且级联成两级;然后针对单粒子瞬态,将延迟单元嵌入在锁存器内部并与级联C单元构成时间冗余;最后选择基于施密特触发器的电路作为延迟单元.实验结果表明,相比已有的加固设计,该锁存器不存在共模故障敏感节点,还能容忍时钟电路中的单粒子瞬态;版图面积、功耗和时钟电路功耗分别平均下降30.58%,44.53%和26.51%;且该锁存器的功耗对工艺、供电电压和温度的波动不敏感.

With technology scaling, single event induced soft error has become an important threat to circuit＇s reliability. A single event hardening latch design is proposed based on SMIC 65 nm CMOS technology. First, C-elements which have the function of holding state were used and cascaded into two levels to tolerate single event upset. Then a delay element was embedded in the latch and combined cascaded C-elements to constitute time redundancy to tolerate single event transient. Finally, a circuit based on Schmitt trigger was chosen as delay element. The experimental results show that the proposed latch has no sensitive node to common mode fault, and tolerates single event transient on clock circuit, compared to the referred hardening designs. It also achieves 30.58% reduction in layout area, 44.53% reduction in power, and 26.51% reduction in power of clock circuit, all on average. Moreover, its power is insensitive to process, supply voltage and temperature variations.