基于FPGA的冗余CAN总线通信节点设计

Design of Redundancy CAN Bus Communication Node Based on FPGA

针对航天领域对通信系统可靠性要求高的特点,提出了基于FPGA、SJA1000和PCA82C250的冗余CAN总线通信节点设计。介绍了CAN总线冗余方式的选择原则,详细给出了采用控制器级冗余方式的通信节点硬件设计和FPGA控制程序设计,重点对SJA1000初始化流程、收发报文处理过程、SJA1000错误处理过程和链路热备份条件下的数据选择策略进行了说明。通过FPGA程序仿真,验证了收发报文时SJA1000的控制时序,进行了高低温条件下的节点传输性能测试和冗余数据处理功能测试。测试结果证明,节点工作稳定性高、实时性强,适用于航天和航空等高可靠性要求的领域。

In view of the requirements for high reliability of the communication system in aerospace field,a design of redundancy CAN bus node is proposed based on FPGA,SJA1000 and PCA82C250.The selection principle of CAN bus redundancy mode is intro- duced,the hardware design of CAN bus node with controller redundancy and the design of the FPGA control program are described in detail.Then,the paper focuses on explaining the initialization flow of SJA1000, message sending/receivintg process, error handling of SJA1000 and data selection strategy under hot backup condition of the link.The control timing of SJA1000 is verified by the simulation result of the FPGA program, and finally the transmission performance test under high and low temperature and the function test of redun- dancy data processing are made.The test results prove that the CAN bus node has high real-time performance and high stability, and the design is suitable for many fields which require high reliability such as space field and aviation field.