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集成电路边界扫描测试系统中测试方式选择模块的电路设计

Circuit Design of Test Mode Selection Module for Integrated Circuits Boundary Scan Testing System
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摘要 集成电路规模的不断增加,使测试的开销在产品总成本中所占的比重越来越大,测试的过程更为复杂,因此对电路芯片需要采用边界扫描测试进行可测性设计。对边界扫描控制器中的测试方式选择TMS模块的功能进行了详细说明,给出了该模块的电路设计方法与步骤。通过与测试软件的结合,能检测芯片间互连线的开路故障、短路故障、固定型故障,以及芯片的内部逻辑功能是否正常。 The increasing scale of integrated circuits makes that the cost of the testing process is increasing in the proportion of the total cost of the product. The testing process of chip is more complex, therefore it is needed to adopt the boundary scan testing which is one of design for testability. The function of test mode selection module in boundary scan controller is demonstrated in this paper, the circuit design method and procedure are given. The combination of boundary scan controller and testing software can detect the open faults, bridge faults, stuck-at faults, and can detect the internal logic function of the chips.
作者 陈翎 潘中良
出处 《装备制造技术》 2016年第7期23-27,共5页 Equipment Manufacturing Technology
基金 广东省自然科学基金(编号:2014A030313441) 广东省科技计划项目(编号:2013B090600063 2014B090901005) 广州市科技计划项目(编号:201510010169)资助
关键词 集成电路 边界扫描 TAP控制器 测试方式选择 integrated circuits boundary scan TAP controller test mode selection
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参考文献9

  • 1陈光禹,潘中良.可测性设计与技术[M].北京:电子工业出版社,1997.
  • 2W.Dghais, J.Rodriguez. New multiport I/O model for power- aware signal integrity analysis[J]. IEEE Trans. on Components Packaging & Manufacturing Technology,2016, 6(3):447-454.
  • 3B.A.Khaled, N.C.Roda, G.Ali. RF performance of SOI CMOS technology on commercial 200-ram enhanced signal integrity high resistivity SOl substrate [J]. IEEE Trans. on Electron Devices, 2014,61(3 ):722-728.
  • 4V.R.Kumar, A.Alam, B.Kaushik. An unconditionally stable FDTD model for crosstalk analysis of VLSI interconnects [J]. IEEE Trans. on Components, Packaging & Manufacturing Technology,2015,5( 12): 1810-1817.
  • 5K.Karmarkar, S.Tragoudas. On-chip codeword generation to cope with crosstalk[J]. IEEE Trans. on CAD,2014,33(2): 237-250.
  • 6IEEE Std1149.1-2001,IEEE standard test access port and boundary-scan architecture[S]. 2001.
  • 7F.Farnaz, N.Bahareh, T.Fatemeh. A new approach to model the effect of topology on testing using boundary scan[J]. Journal of Electronic Testing, 2015,31 ( 3 ) :301-310.
  • 8L.Y.Ungar. Boundary scan as a system-level diagnostic tool [J]. IEEE Instrumentation & Measurement Magazine,2013,16 (4): 8-15.
  • 9B.Terry. Considerations in the design of a boundary scan runtime library [J]. IEEE Instrumentation & Measurement Magazine, 2014,17(4):27-30.

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