适于16纳米及以下技术代的新型器件研究-2013年度总结报告

Research on Novel Devices for 16nm Technology Node and Beyond

针对半导体器件进入16 nm及以下技术代将面临的可制造性难度大、功耗限制、性能退化等核心问题,重点开展了新型围栅纳米线器件、新型超低功耗TFET器件、高迁移率沟道器件、闪存器件以及纳米尺度器件的可靠性及涨落性研究,为新型器件在将来纳米集成电路中的应用奠定了基础。在纳米线器件研究方面,设计了侧墙转移法和TMAH各向异性腐蚀法制备超精细硅纳米线的可控工艺,并进行了实验验证;建立了自限制氧化法硅纳米线制备工艺理论模型,可对工艺进行精确预测;提出了一种原子层掺杂结构可有效调控纳米线器件的阈值电压,同时避免了迁移率的损失;研究了纳米线器件中的GIDL电流机制,提出了抑制GIDL电流的优化方法;提出了一套新的器件-电路优化设计方案,针对纳米线器件在数字电路、模拟/射频电路中的应用分别进行优化设计,得到了相应的设计窗口。在新型低功耗器件研究方面,提出了一种结调制型TFET,显著提升了器件的亚阈特性和开态电流;通过引入pocket层进一步优化了器件结构,实验制备获得了非常低的SS(36mV/dec)和高的开态电流。提出了一种隧穿触发注入场效应晶体管,能同时实现高开态电流、低泄漏电流和陡直的亚阈特性。在纳米尺度MOS器件的可靠性与涨落性研究方面,提出了由AC NBTI引入的工作循环间涨落的两种重要来源的表征方法,实验发现了AC NBTI退化及其涨落的频率依赖性的新现象,建立了物理模型。研究了多栅新器件中的AC RTN,发现比平面器件中的AC RTN活跃程度增强。提出了一种新的AC RTN表征方法,可拓展RTN的栅压探测范围区域。在高迁移率器件研究方面,提出了两种氮等离子体处理方法来提高栅介质/沟道界面质量,进行了实验验证;采用P/Sb共注入技术既有利于提升Ni Ge薄膜质量,也利于电学性能的提升。针对工艺集成中的关键工艺,对锗刻蚀技术进行了实验研究,得到了适于锗的优化刻蚀条件;在此基础上建立了一个线性RIE刻蚀模型,得到了实验验证;完成了Ge NMOS和PMOS器件的工艺制备,分析了不同钝化技术对Ge器件的影响。在新型闪存器件研究方面,针对TFETFlash器件的优化器件设计结构,并制备出TFET-FLASH器件,测试结果表明,与传统闪存器件相比,其编程效率提高100倍左右。针对三维闪存技术面临的问题,提出了一种三维围栅结构的TFT陷阱闪存及其NAND型阵列架构,可有效提高闪存存储密度和降低单元成本;并制备了双层围栅TFT闪存原型。测试结果表明,该新型围栅结构TFT闪存在电流开关比、亚阈斜率、迁移率、编程和擦除速度等方面均获得较大改善,并具有多值存储的潜力。

To overcome the problems of manufacturability, power and performance degradation in conventional semiconductor devices when entering 16 nm technology node and beyond, a series of novel devices are investigated for future nanoscale IC applications, including gateall-around nanowire FETs, ultralow-power TFETs, high-mobility channel devices, Flash memory devices, as well as the device reliability and variability. For nanowire FETs： novel spacer transfer and TMAH etching techniques for controllable nanowire formation are proposed and demonstratedtechnology models for self-limiting oxidation of nanowires are developed for precision process predictionan atomic doping structure is proposed for nanowire threshold voltage control and mobility improvementG IDL in nanowire FETs are studied for its further suppressiona new design methodology for device/circuit optimizations is proposed and demonstrated in nanowire FETs for digital and analog/RF applications. For novel ultralow-power devices： a junction-modulated TEFT is proposed for subthreshold and Ion improvementrecord SS of 36 mV /dec and high current are demonstrated by introducing pocket structuresa tunneling-injection FET is proposed for high-Ion, low-Ioff and steeper SS. For device reliability and variability： characterization methods for AC NBTI induced dynamic variability are proposedthe frequency dependence of AC NBTI degradation and variation are observed and modeledA C RTN in multi-gate devices is found have enhanced activity than that in planar FETsa new AC RTN technique is proposed for expanding RTN test window. For high-mobility devices： two plasma techniques for improving gate stack interface are proposed and demonstratedP /Sb co-implantation technique is adopted for improving NiG e film quality and electrical performanceG e etching is experimentally studied and modeled for process optimizationG e NMOS and PMOS devices are fabricated with various passivation techniques. For novel flash memory devices： a new TFET-FLASH device is proposed and fabricated, which have 100 x improvement in programming efficiencya 3D gate-all-around TFT flash and its NAND array are proposed for increasing density and reducing costtwo-level gate-all-around TFET prototypes are fabricated, which exhibit enhancement in ON/OFF ratio, SS, mobility, programming/erasing speed and the potential for multi-bit storage.