基于130nm CMOS工艺抗单粒子翻转和单粒子瞬态加固技术研究

The Research of SEU and SET Preventing Based on 130nm CMOS process

在空间辐射环境下,CMOS集成电路易受到单粒子翻转和单粒子瞬态的影响,可导致器件功能异常。文章首先分析了几种典型的加固技术,并从触发器的电路结构和物理版图出发,提出了一种基于130nm CMOS工艺抗单粒子翻转和单粒子瞬态脉冲的触发器单元加固设计方法。并结合设计方法,实现了抗辐射加固触发器的设计,通过仿真分析验证了设计的正确性。

In the space radiation environment,the CMOS integrated circuit was easy to be influenced by SEU and SET,leading to the abnormal function of the device. In this paper,several typical SEU / SET-hardened techniques are analyzed firstly. From the point of the circuit structure and physical layout of the flip-flop,a method of SEU and SET preventing flipflop design based on 130 nm CMOS process is proposed. Secondly,the design of the rad hard flip-flop is realized with reference to the design method. As a result,the correctness of the design has been verified by simulation analysis.