6.25 Gb/s快速锁定时钟数据恢复电路

A 6.25 Gb/s Quick-Lock Clock and Data Recovery Circuit

基于65nm CMOS工艺,设计了一种6.25Gb/s时钟数据恢复电路（CDR）。该CDR采用基于相位插值的双环结构和带有快速锁定算法的2阶积分环路实现,支持半速、全速、倍速3种工作模式。其抖动传输带宽在2-7MHz范围内可调,相位插值精度为2.8°,DNL为1.1°,INL为5.6°。在频差为1.0×10^-3时,其锁定速度较传统CDR提高了1倍以上,可应用于满足PCI-E、RAPIDIO协议、短期爆发性传输数据的高速串行接口领域。

A 6.25Gb/s clock and data recovery（CDR）circuit was designed in 65 nm CMOS process.This CDR was realized by a dual-loop architecture with phase-interpolator（PI）and a 2nd order digital loop filter with quicklock algorithm.It supported three modes of half rate,full rate and double rate.The jitter transfer bandwidth of the CDR could be programmed from 2to 7 MHz.The phase resolution of PI was 2.8°.The simulated DNL was 1.1°,and the INL was 5.6°.The locking speed was increased twice as much as the traditional one＇s when the frequency offset was 1.0×10^-3.This CDR can be used in the applications of SerDes which are needed to meet some specifications like PCI-E or RAPIDIO and to transmit data with short-term and explosive mode.