摘要
在宽带分频器中,采用电流模逻辑-D触发器(CML-DFF)结构,加入了并联峰化电感和频率调节电路。分析了CML-DFF分频器的基本工作原理,引入了一种新颖的分析模型。以此模型为基础,设计了一种带峰化电感的宽带可调CML-DEF分频器,提高了电路的设计效率,优化了电路性能。采用TSMC 90nm射频CMOS工艺仿真,结果显示,在0dBm输入信号下,分频器电路的可调节频率锁定范围为3-46.5GHz,芯片面积小于0.22mm^2,功耗仅为6.7mW。
Current mode logic D flip-flop(CML-DFF)structure was applied in a wide-band tunable frequency divider.Parallel shunt peaking inductor and novel frequency tuning circuits were added.The basic operating principle was analyzed.A novel design method for this divider based on an analytical model was introduced to increase the design efficiency,and the divider had been optimized.This divider was designed in TSMC 90 nm CMOS RF process.Post-layout simulation results showed that the proposed divider had achieved a tunable locking range of 3-46.5GHz with 0dBm input power.The area of the chip was 0.22mm^2,and its power consumption was only 6.7mW.
出处
《微电子学》
CAS
CSCD
北大核心
2016年第4期515-518,共4页
Microelectronics
基金
国家自然科学基金资助项目(61201040)
111引智计划资助项目(B14010)
关键词
分频器
并联峰化
电流模逻辑-D触发器
电路建模
Frequency divider
Shunt peaking
Current mode logic D flip-flop
Circuit modeling