时间交织ADC时间失配后台数字校准算法

Background Digital Calibration Algorithm of Timing Skew for Time-Interleaved ADC

提出了一种数字后台校准算法,用于校准时间交织模数转换器(Time-Interleaved Analog-to-Digital Converter,TIADC)的时间失配误差。该算法是基于对输入信号统计的思想,在后台通过分析输入信号的统计特性获得误差信息,再反馈到多相时钟产生器,形成反馈环路,达到校准的目的。该算法硬件消耗小,对输入信号的频率没有限制,可以扩展到任意通道数。对于一个8通道12位TIADC,当输入信号频率fin/fs=0.487时,MATLAB仿真结果表明,采用该算法校准后,SNR从校准前的33.8dB提高到74.0dB,证明了该校准算法的有效性。

A digital background calibration algorithm to calibrate the timing mismatch in time-interleaved analogto-digital converter（TIADC）was presented.The algorithm was based on statistical characteristics of the input signal,adding error information obtained by analyzing the statistical properties to the multi-phase clock generator to form a feedback loop for purpose of calibration in background.The proposed calibration had low hardware resource consumption and no restriction on the input signal frequency,and could be extended to arbitrary number of channels.Simulation of a 8-channel 12-bit TIADC with MATLAB showed that the SNR rose from 33.8dB to 74.0dB at the input frequency fin/fs=0.487 after calibration.Therefore,the effectiveness of the algorithm had been verified.