摘要
针对G3-PLC物理层信道编码的要求,设计了一种RS译码器。为了解决译码过程中有限域乘法器存在的连线复杂、运算速度慢等问题,设计了一种查表运算。采用该查表运算可以快速实现有限域的乘法运算,并且可以简化Berlekamp-Massey(BM)迭代过程中的求逆运算,使得用传统的BM迭代就可以高效地实现RS译码。结合FPGA平台,利用Verilog硬件描述语言和Vivado软件对译码器进行设计与实现。时序仿真结果与综合结果表明,该译码器资源占用率低,能够在100 MHz系统时钟下进行有效译码。
A kind of RS decoder is designed according to the requirements of G3-PLC physical layer channel encoding. A table-referring is de- signed in order to solve the problems such as complex connections, slow speed operation that exist in finite field multipliers. Using the look-up table operation can quickly realize the finite field multiplication, simplify the Berlekamp-Massey iterative, and efficiently realize the RS deco- ding with traditional BM iterative. On the FPGA platform, the design has been implemented by using the Verilog hardware description language and Vivado software. Timing simulation and synthesis results indicate that the decoder has low resource utilization and can efficiently work un- der the 100 MHz system clock.
出处
《微型机与应用》
2016年第17期68-71,共4页
Microcomputer & Its Applications
