摘要
针对目前正则表达式匹配中约束重复问题所带来的空间消耗爆炸以及失配等问题,基于FPGA设计了一种硬件约束重复检测匹配模块,该模块与基于并联ROM的XFA匹配模块相结合,可以快速实现约束重复的检测和匹配。通过定义约束重复参数存储器,计数模块仅消耗少量的硬件资源即可实现约束重复的检测匹配。实验中计数模块可实现Gbps的吞吐量,同时使正则表示式规则存储空间压缩50%以上。
Aiming at the space explosion and mismatching problems posed by complex constraint repetitions in regular expression.This paper designs a FPGA- based hardware constraint repetition inspection block. Combining with the interleaved ROM block, this block can quickly achieve constraint repetition detection and matching. By defining constraint- repetition- parameter- memory, the counting block consumes only a small amount of hardware resources to achieve constrained duplicate detection matches. Experimen-tal results for module that the counting block can reach Gbps throughput and the regular expression rule storage space compression by more than 50 %.
出处
《电子技术应用》
北大核心
2016年第9期47-50,54,共5页
Application of Electronic Technique
基金
国家自然科学基金项目(61402531)
陕西省自然科学基金项目(2014JQ8307
2015JQ6231)