期刊文献+

一种针对可重构处理器流水线简化编程的设计范式

A Design Pattern Targeting to Simplifying Pipeline Design Used on Course-Grained Reconfigurable Processor
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摘要 提出了一种面向可重构处理器流水线的设计范式,并在clang编译架构的基础上添加新的语法,使得用新语法编写流水线程序的时候,能把代码量压缩为原来的10%~20%,并且让代码结构更加清晰和便于理解. This paper propose a new design pattern for simplifying the pipeline design used on Course-Grained Reconfigurable Processor and develop a new compiler based on the clang system. Experiment results show that the amount of code decrease to 10%~20% after applying this designed pattern. Futher more, the new design pattern makes the code clearer and more comprehensive.
出处 《微电子学与计算机》 CSCD 北大核心 2016年第9期6-9,共4页 Microelectronics & Computer
关键词 可重构处理器 流水线 设计范式 reconfigurable processor pipeline design pattern
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参考文献6

  • 1Mirsky E, I)eHon A. MATRIX: a reconfigurable compu- ting architecture with eonfigurable instruction distribution and deployable resources]-C~//Ft~As for Custom Compu- ting Machines, 1996. IEEE Symposium on. Napa Vally, IEEE, 1996: 157-166.
  • 2Gordon M L, Thies W, Amarasinghe S~ Exploiting coarse grained task, data, and pipeline parallelism in stream pm- grams[J]. ACM SICOPS Operating Systems Review,2006, 40(5) : 151-162.
  • 3楼杰超,绳伟光,何卫锋,毛志刚.异构粗粒度可重构处理器的自动任务编译器框架设计[J].微电子学与计算机,2015,32(8):110-114. 被引量:1
  • 4Dieffenderfer J N, Kalla R N. Ping-pong data buffer for transferring data from one data bus to another data bus: US. Patent 5,224,2131-P~. 1993-06-29.
  • 5Lattner (2. LLVM and Clang.. Next generation compil- er technology[C~//The BSD Conference. Canada, Out- awa,2008. 1-2.
  • 6International organization for standardization, ISO/IEC 9899 ~ 1999, Programming Languages-- C[S]. Geneva, Switzerland, ISO, 1999.

二级参考文献11

  • 1MirskyE,DeHon A. MATRIX: a reconfigurable com-puting architecture with configurable instruction distri-bution and deployable resources [C]//IEEE FCCM.NaPa Valley, CA : IEEE, 1996 : 157-166.
  • 2Hauck S,DeHon A. Reconfigurable computing : thetheory and practice of FPGA-based computing [M].Morgan Kaufmann; 2007.
  • 3Miyoshi T,Kawashima H. Terada. A coarse grainreconfigurable processor architecture for stream pro-cessing engine [C]//Proceedings of the 2011 Interna-tional Conference on FPL. Chania:IEEE,2011:5-7.
  • 4Baumgarte V, Ehlers G, May F, et al. PACT XPP: aself-reconfigurable data processing architecture [J].The Journal of Supercomputing, 2003, 26 ( 2 ):167-184.
  • 5Ebeling C, Cronquist D C, Franklin P, et al. Rapid: aconfigurable architecture for compute-intentive applica-tions [EB/OIJ. [2014-10-30]. http://www. cs. Wash-ington. edu/research/lis/rapid/overview. 2006.
  • 6SinghH, Lee M,Lu G,et al. MorphoSys : case studyof a reconfigurable computing system targeting multi-media applications [C]//Proc Design Automation Con-ference. [s. 1. J : IEEE, 2000:573-578.
  • 7YanL,Wu B,Wen Y,et al. A reconfigurable proces-sor architecture combining multi-core and reconfigu-rable processing units [C]//IEEE CIT. Bradford:IEEE, 2010:2897-2902.
  • 8VenkataramaniG,Najjar W, KurdahiF,et al. A com-piler framework for mapping applications to a coarse*grained reconfigurable computer architecture[C]//ProcCASES 01. [s. 1. ]. ACM,2001 :116-125.
  • 9Nah J, Lee J, Kim H, et al. An OpenCL optimizingcompiler for reconfigurable processors [C]//Proceed-ings of the 2013 International Conference on Field-Pro-grammable Technology. Kyoto: IEEE, 2013 : 184-191.
  • 10YINC, YIN S, LIU L, et al. Compiler framework forreconfigurable computing system[C]. IEEE ICCCASMipitasJEEE, 2009 : 991-995.

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