CSRe内靶定时探测器系统容性负载隔离电路设计

Capacitive-Load Isolation Techniques in Timing Detector of CSRe Internal Target

针对定时电路驱动容性负载出现的过冲、振铃等问题,提出采用容性隔离技术,在不影响电路增益、带宽的情况下,使电路具有一定的容性负载能力,提高稳定性。通过构建电路模型,从数学角度分析了电路不稳定的原因,并应用实验证明了容性负载隔离技术的合理性。容性负载隔离技术可以有效消除容性负载电路带来的增益凸峰及恶化的频率响应。

Capacitive- load isolation technique was proposed to improve the stability and capacitive load ability of the timing detection system in internal target of CSRe. This technique can solve the overshoot and ringing problems of the circuit, without affecting its gain and bandwidth. By constructing the circuit model, the cause of the instability of the circuit is analyzed mathematically, and the rationality of the capacitive - load isolation techniques is proved in the experiment. It is demonstrated that the capacitive -load isolation technique can ef- fectively eliminate the gain hump and the deteriorative frequency response caused by the capacitive load.