新型时钟管理电路模型分析与参数设计

Model analysis and parameter design for new-type clock management circuit

现今,电子产品的功能越来越复杂,随之而来在电路板设计中会选用多种类型芯片,比如微处理器、ADC、存储器、接口芯片等。这种情况下就需要时钟管理电路实现对多路时钟在频率、相位、占空比、抖动指标上的管理,为每种芯片提供不同属性的工作时钟。本文提出一种基于时钟芯片的新型时钟管理电路,进行总体方案设计,重点对电路中的锁相环的重要环节模型及电路整体模型进行分析,归纳了电路参数选择方法及其与系统指标之间关系,为最终电路详细设计和程序配置的提供参考依据。

Nowadays,the functions of electronic products are more and more complex,and then different kinds of chips,such as MCU,ADC,memories,interface chips and so on,will be selected in the PCB design.In this case,the clock management circuit is needed to provide different working clocks for each chip.It manages several clock signals in part of frequency and phase,etc,and improves signals in part of cycle duty,jitter,etc.The new-type clock management circuit based on the clock chip is designed in this paper,which consist of the clock management circuit unit and the clock management IP core in the control unit.The important components and the whole circuit are selected to build math models and be analyzed.The method for selecting circuit parameters and the relationship between circuit parameters and system parameters are concluded,which are the references for the detailed circuit design and software configuration.