摘要
针对Sigma-Delta ADC在实现高精度的同时如何降低系统功耗这一问题,通过进行建模分析,得出满足精度需求的最低性能指标。并对二阶Sigma-Delta调制器的非理想因素进行数学建模分析,在满足ADC精度的同时对ADC组成模块的最低性能指标进行分配,利用SDtoolbox进行仿真验证。基于CSMC 0.5μm CMOS工艺,在5 V电源电压下,对调制器进行了电路级设计。结果显示在模块最低性能时,调制器输出信号的带内信噪比为83.5 d B,总功耗为1.8 m W。
The analog-to-digital converter （ADC） is the necessary interface for analog signal to digital signal conversion. The minimum performance index of the sigma-delta ADC while meeting the precision demand are ob- tained by modeling in order to reduce the power consumption of the system while maintaining high precision. The mathematical modeling analysis of the non-ideal factors of a second-order Sigma-Delta modulator is performed, and the distribution of minimum performance indicators of the ADC module is simulated with SDtoolbox. Based on 0.5 μm CMOS CSMC process and under the 5 V power supply voltage, this paper presents the modulator circuit design. The results show that the in-band signal-to-noise ratio is 83.5 dB, and total power consumption is 1.8 mW at mini- mum performance of the modulator.
出处
《电子科技》
2016年第9期136-138,144,共4页
Electronic Science and Technology
基金
江苏省自然科学基金资助项目(BK2012792)
