基于FPGA的RS编码的设计与实现

The Implementation and Design of Reed-Solomon Encoder Based on FPGA

RS码是线性分组码中一种典型的纠错码,它既能纠正随机错误,也能纠正突发错误,在现代通信领域中越来越受到重视。论文在分析RS编码原理的基础上,主要研究了基于FPGA的RS编码器的组成和结构,并使用VHDL语言和RAM模块设计了数据转换模块,最后在Quartus II 8.1软件环境下进行功能仿真,仿真结果与MTALAB编码结果对比一致,验证该设计的正确性,该设计方法在大容量通信系统中得到实际验证。

RS code is an important linear block code widely used in modern digital communications. It can correct both random and bursting errors. In this paper, we analyze the theory of Reed-Solomon, and research the RS encoder composition and structure based on the FPGA, and design data conversion module with the language of VHDL and RAM module, and realize the function simulation in the Quartus II 8.1 software environment, simulation results agree with MTALAB theoretical analysis to verify the correctness of this design. The method is given in large capacity communication system.