摘要
随着航空电子体系架构的日益更新,航空机载总线技术得到了飞速发展。时间触发以太网作为新一代的航空总线适合在分布式综合模块化电子系统中应用。时钟同步机制是该网络的核心技术,通过该技术建立的高精度全局同步时钟是保障TTE的数据通信强实时性和确定性的先决条件。本文在分析研究TTE时钟同步算法的基础上,提出了符合SAE AS6802协议标准的TTE端系统的时钟同步机制的设计方案,并在FPGA硬件上得以实现。
With the increasing update of avionics architecture, airborne bus technology is developing rapidly. As a new generation of avionics bus, time-trigger Ethernet is suitable for applications in distributed integrated modular electron systems. Clock synchronization mechanism is the core technology of network, which establishes a global high-precision synchronous real-time clock,which is a prerequisite of strong real-time and certainty data communication of TTE. The article is based on the in-depth analysis and study of the TTE clock synchronization algorithm, and it proposes a design method based on TTE end system clock synchronization mechanisn~ This method meets SAE AS6802 protocol standard of the network system and is applied in FPGA hardware.
出处
《航空电子技术》
2016年第3期30-35,共6页
Avionics Technology
关键词
时间触发
全局同步时钟
时钟同步算法
time-trigger（TT）
global synchronous clock
clock synchronization algorithm
