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面向异构多核系统芯片的高效动态带宽划分方法 被引量:1

Improving System Performance in Heterogeneous MPSoC Systems via Dynamic DRAM Bandwidth Allocation
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摘要 针对异构MPSoC中各主设备频繁争抢有限访存带宽、请求相互干扰、严重影响系统性能的问题,提出一种基于限流的动态DRAM带宽分配机制——TDBA.首先实时监测主设备访存特性,通过访存干扰程度评估将主设备分组;然后对造成严重干扰的主设备设置带宽限流阈值来防止其过度争抢带宽,并根据系统带宽使用情况动态调整该阈值,同时优先计算密集主设备的请求以进一步提高系统性能.将TDBA应用于真实异构MPSoC系统的实验结果表明,TDBA可以有效地降低访存干扰,明显提高系统性能. In the era of heterogeneous MPSoC, more and more cores are coschedule on a single chip to share DRAM bandwidth and exacerbates the contention problem on DRAM bandwidth. The inter-core interference significantly aggravates the memory access latency, leading to poor system performance and fairness. In this paper, we propose a Throttling based dynamic DRAM bandwidth allocation mechanism(TDBA) to address the problem. TDBA profiles cores' memory access characteristics at run-time and estimate their interference at DRAM memory to divide them into either compute-intensive cluster or memory-intensive cluster. Meanwhile, TDBA constraints cores in memory-intensive cluster as if to prevent them from dominating DRAM bandwidth usage and starving the cores in compute-intensive cluster. Furthermore, TDBA prioritizes cores in compute-intensive cluster to allow them to quickly resume computation, which further improves system per-formance. We implemente TDBA in a real heterogeneous MPSo C system. Experimental results show that the mechanism significantly improves system performance.
出处 《计算机辅助设计与图形学学报》 EI CSCD 北大核心 2016年第10期1786-1795,共10页 Journal of Computer-Aided Design & Computer Graphics
基金 国家"核高基"科技重大专项(2009ZX01029-001-002)
关键词 异构多核系统芯片 多核应用 访存干扰 带宽限流 HMPSoC multicore application interference bandwidth throttling
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