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重心坐标插值的三角形着色算法硬件实现 被引量:2

Implementation of triangle tinting algorithm based on the center of gravity coordinate interpolation
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摘要 针对三角形的平滑着色技术,设计并实现一种三角形颜色插值的硬件加速器。根据三角形建立单元输入的三角形顶点数据,利用边界方程计算三角形的面积以及面积倒数。通过扫描转化模块筛选出每个三角形覆盖的有效像素块,最后利用三角形建立单元得到的边界方程值与三角形面积倒数值,通过插值模块实现经过扫描转换模块处理后的三角形内所有片元的颜色插值。测试结果表明,该加速器最大工作频率可达约为222.2 MHz,能够实现嵌入式GPU中图形平滑着色的要求。 A hardware accelerator for triangle color interpolation is designed and accompnsnea. The area of the triangle and area reciprocal are calculated by using the boundary equation with triangle vertex data coming from triangular element. The effective pixel block of each triangle is selected by using the scan conversion module. The boundary value equation and reciprocal of the triangular area obtained from Triangle building unit are then used, and color interpolation of all slice elements in triangle processed by scan conversion module is achieved by using the interpolation module. Testing results show that the accelerator can achieve maximum working frequency of 222.2 MHz, which can achieve embedded GPU graphics smooth rendering.
作者 杜慧敏 季凯柏 蒋忭忭 郭冲宇 DU Huimin JI Kaibo JIANG Bianbian GUO Chongyu(School of Electronic Engineering, Xi'an University of Posts and Telecommunications, Xi'an 710121, China)
出处 《西安邮电大学学报》 2016年第5期39-42,共4页 Journal of Xi’an University of Posts and Telecommunications
基金 国家自然科学基金重点资助项目(61136002) 西安市科技发展计划资助项目(CXY1440(10))
关键词 重心坐标插值 平滑着色 嵌入式GPU gravity co-ordinate interpolation, smooth shading, embedded GPU
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  • 1MOSMONDOR M,KOMERICKI H,PANDZIC I.3D Visualization on mobile devices[J/OL].Handbook of Research on User Interface Design&Evaluation for Mobile Technology,2006,32(2-3):181-191[2016-05-23].http://dx.doi.org/10.1007/s11235-006-9137-3.
  • 2TOMAS A M,ERIC H.实时计算机图形学[M].普建涛,译.2版.北京:北京大学出版社,2004:88-89.
  • 3EDWARD A,DAVE S.交互式计算机图形学[M].6版.张荣华,译.北京:电子工业出版社,2011:107-109.
  • 4郭安泰,郭立,杨毅,吴思.一种图形光栅的硬件实现算法[J].中国图象图形学报,2009,14(1):176-182. 被引量:2
  • 5ANAND V B.Computer Graphics and Geometric Modeling for Engineers[M]//New York:John Wiley&Sons,1996:55-68.
  • 6BROWN R A.Barycentric Coordinates as Interpolants[EB/OL].[2016-05-23].http://arxiv.org/pdf/1308.1279v3.
  • 7SKALA V.Duality,barycentric coordinates and intersection computation in projective space with GPU support[J/OL].Wseas Transactions on Mathematics,2010,9(6):407-416[2016-05-23].https://otik.uk.zcu.cz/xmlui/bitstream/handle/11025/11337/Skala_2010_NAUN-journal.pdf?sequence=1.
  • 8焦继业,穆荣,郝跃,刘有耀.面向移动图形顶点处理器的高性能低功耗定点特殊函数运算单元设计[J].电子与信息学报,2011,33(11):2764-2770. 被引量:8
  • 9牛涛,沈海斌.基于分段二次插值的初等函数逼近低成本设计[J].计算机工程,2013,39(8):285-287. 被引量:3
  • 10SUN C H,TSAO Y M,LOK K H.Universal rasterizer with edge equations and tile-scan triangle traversal algorithm for graphics processing units[C/OL]//ICME’09 Proceedings of the 2009IEEE international conference on Multimedia and Expo,NJ:IEEE,2009:1358-1361[2016-05-23].http://dx.doi.org/10.1109/ICME.2009.5202755.

二级参考文献27

  • 1James D.Foley等著.计算机图形学原理及实践:C语言描述[M].第2版.唐泽圣,董上海等译.北京:机械工业出版社,2004.
  • 2Akeley Kurt, Jermoluk Tom. High Performance polygon rendering [J]. Computer Graphics,1988, 22(4) : 239-246.
  • 3Kugler Ander. The setup for triangle rasterization [ A ]. In: Proceedings of the 11^th Eurographics Workshop on Computer Graphics Hardware [ C], Poitiers, France, 1996:49-58.
  • 4Yu Jiang-yi. Scan Converting Triangles-Lecture 06 CISC 440/640 Spring 2007 [ EB/OL]. http://www. cis. udel. edu/- yu/Teaching/ CISC4 40_07S/handouts/Lecture06. pdf.
  • 5Pineda Juan. A parallel algorithm for polygon rasterization [ A]. In: Proceedings of ACM SIGGRAPH 1988 [ C ], Atlanta, Georgia, USA, 1988 : 17-20.
  • 6Wailer Marcus, Ewins Jon, White Martin,et al. Efficient primitive traversal using adaptive linear edge function algorithms [J]. Computer Graphics, 1999,23 : 365-375.
  • 7PowerVR . PowerVR White Paper: 3D Graphical Processing[ EB/ OL]. http ://www. powervr., com/pdf/TBR3D. pdf.
  • 8McCormack Joel, McNamara Robert. Tiled polygon traversal using half-plane edge functions [ A]. In: Proceedings of the 2000 SIGGRAPH/EUROGRAPHICS Workshop on Graphics Hardware [ C ] , Interlaken, Switzerland, 2000 : 15-21.
  • 9Park Woo-chan, Lee Kil-whan, Kim II-san,et al. An effective pixel rasterization pipeline architecture for 3D rendering processors [ J]. IEEE Transactions on Computers, 2003,52 ( 11 ) : 1501-1508.
  • 10ATI Technologies Incorporation Radeon X800: 3D Architecture Whitepaper [ EB/OL ] . http ://ati. de/products/radeonx800/Radeon X800 Architecture WhitePaper. pdf.

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