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Low complexity SEU mitigation technique for SRAM-based FPGAs

Low complexity SEU mitigation technique for SRAM-based FPGAs
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摘要 An internal single event upset(SEU)mitigation technique is proposed,which reads back the configuration frames from the static random access memory(SRAM)-based field programmable gate array(FPGA)through an internal port and compares them with those stored in the radiationhardened memory to detect and correct SEUs.Triple modular redundancy(TMR),which triplicates the circuit of the technique and uses majority voters to isolate any single upset within it,is used to enhance the reliability.Performance analysis shows that the proposed technique can satisfy the requirement of ordinary aerospace missions with less power dissipation,size and weight.The fault injection experiment validates that the proposed technique is capable of correcting most errors to protect spaceborne facilities from SEUs. An internal single event upset(SEU)mitigation technique is proposed,which reads back the configuration frames from the static random access memory(SRAM)-based field programmable gate array(FPGA)through an internal port and compares them with those stored in the radiationhardened memory to detect and correct SEUs.Triple modular redundancy(TMR),which triplicates the circuit of the technique and uses majority voters to isolate any single upset within it,is used to enhance the reliability.Performance analysis shows that the proposed technique can satisfy the requirement of ordinary aerospace missions with less power dissipation,size and weight.The fault injection experiment validates that the proposed technique is capable of correcting most errors to protect spaceborne facilities from SEUs.
作者 姜润祯 王永庆 冯志强 于秀丽 JIANG Run-zhen WANG Yong-qing FENG Zhi-qiang YU Xiu-li(School of Information and Electronics, Beijing Institute of Technology, Beijing 100081, China Beijing Institute of Astronautical Systems Engineering, Beijing 100076, China)
出处 《Journal of Beijing Institute of Technology》 EI CAS 2016年第3期403-412,共10页 北京理工大学学报(英文版)
基金 Supported by the National High Technology and Development Program of China(2013AA1548)
关键词 static random access memory (SRAM) field programmable gate array (FPGA) single event upset (SEU) low complexity triple modular redundancy SCRUBBING static random access memory (SRAM) field programmable gate array (FPGA) single event upset (SEU) low complexity triple modular redundancy scrubbing
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