自适应非线性流采样算法的硬件实现

The Hardware Implementation of Adaptive Non-Linear Sampling Algorithm

针对自适应非线性流采样(DISCO)算法硬件实现面临的一系列挑战,设计了利于硬件处理的改进算法,采用多查找表结构和"归一化"方法进行处理,完成了正确性仿真和基于现场可编程门阵列(FPGA)平台的原型验证.实验结果表明,改进算法能够实现40 Gbit/s链路的线速每流统计,消耗FPGA上的硬件逻辑资源较少,并且平均相对误差和最大相对误差均与基准DISCO算法性能接近.

In flow-based passive measurement of the Internet,the measurement of flow size and flow volume is a basic requirement. To resolve the contradiction of increasing network link speed and small-sized fast memory chipset,a non-linear sampling algorithm which is named discrete counting（ DISCO）,was proposed in related research work. In order to meet the need of wire-speed network traffic measurement,DISCO is suggested to be implemented by hardware approaches,such as field-programmable gate array（ FPGA）. However,DISCO involves complex calculations with high precision,which give rise to a series of challenges in hardware acceleration. To solve the problems,a hardware-friendly refined algorithm was designed,which employs multiple lookup tables and a normalization method. Simulation was conducted to verify the validity of the refined algorithm. An FPGA-based prototype was made. Experiments show that the refined algorithm can achieve wire-speed flow measurement of a 40 Gbit / s link,with small hardware logic resources consumption of FPGA. The average relative error and maximum relative error of the refined DISCO algorithm are close to the original one.