基于高性能FPGA的合并单元设计与实现

Realization of the critical technologies merging unit based on FPGA

介绍了在合并单元功能实现中FPGA高实时性、高精度、高可靠性的应用,重点介绍了采用FPGA实现合并单元点对点SV报文收发的方法,通过FPGA实现合并单元时间同步及守时的原理及方法。在点对点SV报文收发过程中,FPGA控制DM9000C,将接收到的SV报文放在FIFO中缓存,并通过内部定时器对接收的报文打时标,在SV报文接收的间隙,FPGA配合CPU精确地控制SV报文的发送时间,保证其离散性控制在100 ns以内。在对时状态下,通过FPGA解析B码和和1588对时信息,保持合并单元的时间同步,并采用跟随算法记录秒脉冲时间间隔。在丢失外部同步信号时,FPGA时间同步模块无缝切换到守时状态,并能在长时间内保证合并单元的守时精度。

This paper introduces the features of high real-time performance, high precision, and high reliability of FPGA in merging unit function implementation. It mainly introduces the point-to-point SV message sending and receiving method by adopting FPGA. The method and the principle of realizing merging unit time synchronization and punctuality via FPGA. In the process of point-to-point SV sending and receiving, FPGA controls DM9000 C, caches the received message of SV in FIFO, and marks the time scale of the received message through the internal timer. During the interval of SV message receiving, FPGA, cooperating with the CPU, controls SV packet delivery time precisely, and guarantees its discreteness not more than 100 ns. In synchronism state, B code and 1588 time synchronization information are parsed through FPGA to accurately keep time synchronized of the merging unit, and the following algorithm is used to record the interval of second pulse time. When the external synchronization signal is lost, FPGA time synchronization module will be switched to punctuality state, which can keep punctuality precision of merging unit in a long time.