基于硬件描述语言的可逆逻辑描述与验证方法

Reversible Logic Description and Verification Based on Hardware Description Language

针对可逆逻辑综合在设计较大规模可逆逻辑电路中遇到的瓶颈,文中借助于硬件描述语言的高层次抽象描述能力以及现有EDA平台的仿真验证功能,通过在模块中添加辅助位的方法,使得模块在具有相应功能的同时具备可逆性,并对模块进行实例化,实现对可逆算术逻辑单元的描述与综合。仿真验证表明,该方法具有一定的可行性和有效性。

The high level abstract description capability of the hardware description language and simulation capability of the current EDA platform are combined to resolve the bottleneck in the design of large-scale reversible logic circuits by reversible logic synthesis. Service bits are added to the module, which offers the module both a corre- sponding function and reversibility. The module is also instantiated for the reversible arithmetic logic unit to be described and synthesized. The simulations show that the proposed method is feasible and effective.