基于NIOS Ⅱ软核的数字频率计实现

Implementation of Digital Frequency Meter Based on Nios Ⅱ Soft-core

本文利用Cyclone IV E系列FPGA芯片内部资源及NIOS Ⅱ软核设计完成一款等精度数字频率计,其测频功能利用Verilog语言实现,对测频模块得到的各项数据利用C语言编程实现,并通过实时运算将数据传送给液晶模块.本设计具有测量带宽大、实现面积小、数据传输可靠稳定等特点,并且由于各部分相互独立,两两之间不相互依赖,系统灵活高效.

In this paper, a precise digital frequency meter was implemented using Cyclone IV E series FPGA chip resources and NIOS II soft-core. Verilog Language was used for the frequency measurement function, while C language was used for the data manipulation. Then the data was transferred to the LCD module based on real-time operations. This design owned the features of large measuring bandwidth, small area and stable data transformation. Also each module in tbe whole system was independent to each other, and the whole system was flexible and highly effective.