摘要
基于CPCI总线和信号采集的相关技术,提出了一种以FPGA为核心的CPCI信号采集板卡的设计。该板卡主要由电源模块、时钟网络、DDRII高速缓存阵列、CPCI通信单元、FMC子卡接口等单元组成。详细描述了板卡软硬件实现的原理,提出了流水线的设计思路,着重介绍了基于乒乓结构的高速DDRII缓存阵列以及CPCI总线的设计思路和实现方式。通过实验验证,高速DDRII缓存阵列可以达到400 Mbit/s的传输速率,PLX9656可工作在66 MHz的时钟下,并且板卡具有较高的稳定性。
Based on the relevant technology of CPCI bus and signal acquisition, a CPCI signal acquisition board design is proposed with the FPGA as the core. The board is composed of a power module, a clock network, a DDRII cache array, a CPCI communication unit, a FMC sub card interface, and so on. This paper gives a minute description of the implementation methods of software and hardware boards, and the design idea of the pipeline is put for- ward, It highlights the structure based on ping-pong of the high-speed DDRII cache array and the design ideas and implementation of CPCI bus. Through experiments, High speed DDRII cache array can achieve the transmission rate of 400 Mbit/s, PLX9656 can also work under the clock of 66 MHz, and the board has a high stability.
出处
《电子器件》
CAS
北大核心
2016年第4期851-855,共5页
Chinese Journal of Electron Devices
基金
基于工业CT固体火箭发动机缺陷定位与分割技术研究项目(61171177)