基于FPGA的可配置IIC总线接口设计

Development of Configurable IIC Bus Interface Based on FPGA

针对传统IIC总线接口的FPGA设计可重用性不高的问题,提出了一种基于FPGA的可配置IIC总线接口设计方案。该方案采用同步有限状态机设计方法和硬件描述语言Verilog HDL,对IIC总线的数据传输时序进行模块化设计,采用Signal Tap II对设计模块进行仿真验证。实验结果表明,该设计接口作为一种主控制器接口,可实现与具有IIC总线接口的从机器件100 kbyte/s和400 kbyte/s的可靠数据传输。该方案具有可重用度高、可配置性强、控制灵活等优点,并已成功运用于工程实践中。

Aimed at lower reusability of FPGA design in traditional bus interface of IIC, one configurable FPGA- based bus interface design of IIC was proposed. Data transmission sequence of IIC bus was designed in modules with finite state synchronous circuit design method and hardware description language of Verilog HDL. The designed modules were simulated, tested and verified by using the data logic analyzer of Signal Tap II. The experimental results show that this interface could reliably achieve the data transmission of 100 kbyte/s and 400 kbyte/s with the slaves using IIC bus interface and it has the advantages of higher reusability, strong configurability, flexible control. Moreover, the designed interface was successfully applied to engineering practice.