大容量弹载数据记录器的设计与实现

Design and Implementation of Large Capacity Missile Borne Data Recorder

提出了一种大容量弹载数据记录器的设计方案,该方案主要完成3路高速图像数据的接收,每个通道的数据带宽为每秒150 Mbyte/s,存储容量为128 Gbyte。设计选用Xilinx公司的FPGA作为主控制器,完成对高速数据的接收,缓存和存储。接收单元采用FPGA内部集成的高速串行收发器RocketIO GTP,单个链路的数据接收速率为3.125 Gbyte/s;缓存单元采用两片DDR2 SDRAM芯片对接收到的高速数据进行乒乓缓存;存储单元采用32片NAND FLASH构成存储阵列,对缓存后的数据进行存储。同时,该记录器能够对存储的数据进行事后读取并进行分析。

A high capacity of the onboard data logger design has been presented, The scheme is mainly completed 3 high-speed image data receiving, each channel＇s data bandwidth is 150 Mbyte/s, the storage capacity is 128 Gbyte. Xilinx＇ s FPGA design selected as the main controller, the completion of high-speed data reception, caching and storage. The receiving unit adopts GTP RocketIO, which is integrated with FPGA, the data receiving rate of a single link is 3.125 Gbyte/s; High-speed data buffer unit two DDR2 SDRAM chips received ping-pong cache;The memory cell is composed of 32 pieces of FLASH NAND, which is stored in the memory array. Meanwhile, the recording device is capable of reading the stored data and analyzed afterwards.