可逆处理器指令流水线的设计与仿真

Design and simulation of pipelining for reversible processor

为实现可逆处理器的指令流水线,提出一种适合可逆指令流水的数据通路图。明确可逆指令流水线的7个阶段(即读指令、指令译码、读寄存器、运算/访问存储器、写寄存器、指令编码、返回指令)以及各阶段任务,分析在可逆约束下指令流水可能遇到的数据冒险和控制冒险,通过转发和阻塞技术解决此类冒险。通过仿真系统验证该指令流水线的正确性,仿真结果表明,该方法能有效实现可逆处理器中的指令级并发,在保证程序功能不变的前提下交换一些指令的位置,显著提高流水线性能。

To design instruction pipeline for reversible processor,a datapath which suited for reversible pipelining was presented.The stages of piplining were identified,which included instruction reading,instruction decoding,register reading,execution and memory access,register writing,instruction encoding,and instruction returning.Data and control harzards were ascertained and solutions to these harzards via forwording and stocking technique were provided,and the validity and performance of piplining was verified by the simulation.Results of simulation show that this method can realize instruction-level parallelism effectively,and finds out that position exchanging of some instructions can improve the performance of the pipeline.