期刊文献+

3D叠层封装集成电路的缺陷定位方法 被引量:1

Defect Localization Method of 3D Stacked-Die Packaged Integrated Circuits
下载PDF
导出
摘要 三维(3D)叠层封装集成电路是高性能器件的一种重要封装形式,其独特的封装形式为失效定位带来了新的挑战.文中融合实时锁定热成像和X射线探测技术,提出了一种3D叠层封装集成电路缺陷定位方法.该方法首先利用X射线探测技术从器件的正面、侧面获取电路内部结构并成像,进而确定芯片的装配位置及面积、芯片叠层层数、引线键合方式;然后利用锁定热成像技术获得缺陷在封装内部传播的延迟信息及在封装内部xy平面上的信息,通过计算不同频率下的相移来确定叠层封装中缺陷在z轴方向的位置信息.对某型号塑料封装存储器SDRAM中缺陷的定位及对缺陷部位的物理分析表明,锁定热成像与X射线探测技术相结合,可以在不开封的前提下进行3D叠层封装集成电路内部缺陷的定位. Three-dimension( 3D) stacked-die package is one of the important package types of high-performance devices. Its unique packaging brings new challenges to defect localization. In this paper,a localization method of defects inside 3D stacked-die packaged integrated circuits,which integrates both lock-in thermography imaging and X-ray detection technology,is proposed. Firstly,X-ray detection technology is used to obtain internal structure of the device horizontally and vertically,and thus the chip location and size,the stack layers and the wire bonding mode inside the package can be determined. Secondly,the propagation delay information of defects inside package and the defect location on xy plane are obtained via lock-in thermography imaging. Then,more exact location information of the defect in z direction is obtained by calculating the phase shift at different frequencies. Finally,some experiments are carried out to discover the localization of defects inside a plastic packaging SDRAM,and the corresponding physical analysis is made. The results show that the integration of lock-in thermography imaging with X-ray detection technology helps localize defects of 3D stacked-die packaged devices without decapping the device.
出处 《华南理工大学学报(自然科学版)》 EI CAS CSCD 北大核心 2016年第5期36-41,47,共7页 Journal of South China University of Technology(Natural Science Edition)
基金 广东省自然科学基金资助项目(2014A030313656)~~
关键词 三维叠层封装 集成电路 缺陷定位 失效分析 3D stacked-die package integrated circuit defect localization failure analysis
  • 相关文献

参考文献4

二级参考文献45

  • 1廖凯.堆叠/3D封装的关键技术之一——硅片减薄[J].中国集成电路,2007,16(5):79-81. 被引量:8
  • 2陆军.3D封装[J].集成电路通讯,2005,23(4):41-47. 被引量:4
  • 3P.Ramm, M.J.Wolf, A.Klumpp, et al. Through silicon via technology:processes and reliability for wafer-level 3D system integration[C]. 2008 Electronic Components and Technology Conference, 2008: 841-846.
  • 4Peter Ramm, Armin Klumpp, Josef Weber, et al. 3D integration technologies[C]. 2009 Symposium on Design, Test, Integration & Packaging of MEMS/MOEMS, 2009: 71-73.
  • 5Rao R. Tummala. SOP: What is it and Why? A New Microsystem-Integration Technology Paradigm-Moore' s Law for System Integration of Miniaturized Convergent System of the Next Decade [J]. IEEE Transactions on advanced packaging, 2004, 27 ( 2 ) : 241-249.
  • 6Rao R. Tummala, Madhavan Swaminathan. Introduction to System-on-Package (SOP) [M].McGraw-Hill Companies, 2008.25-60.
  • 7Gilles Poupon, System on Wafer : Proceedings of the Nicolas Sillon, David Henry, et al. A New Silicon Concept in SiP [J]. IEEE, 2009, 97 ( 1 ) : 60-69.
  • 8M.J.Wolf, P.Ramm, A.Klumpp, et al. Technologies for 3D Wafer Level Heterogeneous Integration [C].2008 Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS, 2008: 123-126.
  • 9Jean-Charles Souriau, Olivier Lignier, Michel Charrier, et al. Wafer Level Processing of 3D System in Package for RF and Data Applications [C].2005 Electronics Components and Technology Conference, 2005: 356-361.
  • 10Linda Katehi, Barry Perlman, William Chappell, et al. Three Packaging architectures Dimensional Integtation and on-wafer for Heterogeneous wafer-scale circuit [R]. University of Illinois, Urbana- Champaign, IL, 2006.

共引文献53

同被引文献57

引证文献1

二级引证文献90

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部