摘要
装箱是FPGA工具设计流程中关键的一步,是综合、工艺映射和布局的桥梁,在很大程度上影响了电路的速度和功耗。基于千万门级FPGA xc5vlx20tff323-2器件,对XST综合工具综合后的网表进行装箱,并把装箱结果转换为XDL格式文件,使用Xilinx工具验证其正确性。
Packing is a key step in the FPGA tool flow that straddles the boundaries between synthesis,technology mapping and placement, and that greatly influences circuit speed, density, and power consumption.In the paper, xc5vlx20tff323-2 device, a 10M-gate FPGA, is described in detail covering the packing of the net list synthesized by XST tool, conversion to XDL file and verification by Xilinx tools.
出处
《电子与封装》
2016年第10期32-35,42,共5页
Electronics & Packaging
关键词
FPGA
装箱
验证
FPGA
packing
verification
