考虑扇出重汇聚效应的组合电路软错误率评估

Re-convergence aware SER estimation for combinational logic circuits

为了准确评估集成电路的软错误率(soft error rate,SER),文章提出一种新颖的电路SER评估方法。通过门级仿真获得逻辑门输出信号,将产生瞬态故障的逻辑门进行故障注入,然后使用考虑扇出重汇聚的敏化路径逼近搜索算法查找不同输入向量下的敏化路径;通过单指数电流源模拟瞬态故障脉冲的产生,并将脉冲在敏化路径上传播,使用脉冲屏蔽模型评估电气屏蔽和时窗屏蔽效应;最后采用该方法计算可得电路总体SER。实验结果表明,由于考虑扇出重汇聚的影响,该方法平均提高8.2%的SER评估准确度。

In order to accurately evaluate soft error rate（SER） of integrated circuits, a novel SER estimation technique for circuits was proposed. After gate-level logic simulation, by reversing the output signal of a particle striking gate cell, the sensitized pa,ths and delay were accurately computed by the re-convergence aware sensitized path search algorithm under different input vectors. Then single event transient pulses were simulated by single-exponential current source model, and by propagating these pulses through the gate cells on sensitized paths respectively, electrical masking and timing masking were precisely evaluated by pulse masking models. Finally, SER of circuits was effectively calculated by the SEN estimation technique. The experimental results show that the SER accuracy is improved by 8.2% on average via the proposed re-convergence aware SER estimation technique.