高速低功耗SRAM体系结构及设计仿真

Design and Simulation of System Structure of High Velocity and Low Power SRAM

提出了一种高速低功耗1M-bit静态随机存储器的体系结构设计,在此体系结构基础上完成了整体电路架构的搭建。同时,运用Hspice模拟电路仿真工具完成了电路系统仿真。在5V电源电压下,采用CSMC 0.35μm工艺模型,地址取数时间为15ns,平均动态功耗为100m A,静态功耗为6m A,实现了静态随机存储器高速、低功耗的良好性能。

A design of a system structure of high velocity low power 1M - bit SRAM is described in this paper, and the construction of circuit is finished on the basis of system structure. At the same time, the simulation of the circuit system is accomplished by Hspice. In the conditions of 5V and CSMC 0. 35（xm process model, with the address access time of 15ns, the average dynamic power of 100mW and the static power of 6mW, good capability of low power and high velocity SRAM are carried out.