期刊文献+

H.264中逆量化逆变换的高层次综合实现

High level synthesis implementation of inverse quantification and inverse transformation in H.264
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摘要 逆变换与逆量化是H.264解码器中的一个重要环节,由于其算法复杂度较高,利用传统的RTL方法设计其硬件电路需要消耗大量的设计时间并经历复杂的验证过程。提出了采用高层次综合的方法进行高效快速的逆变换逆量化硬件模块设计。测试结果表明,该方法可以较快地得到针对FPGA平台的逆变换逆量化硬件模块,同时可对其设计空间进行有效探索,得到满足不同需求的硬件模块。 Inverse transformation and inverse quantization is an important process in H.264 decoder, the complexity of the algorithm leads to a long design time and complex verification procedure when designing in conventional way with RTL language. High level synthesis in involved in this paper to illustrate efficient inverse transformation and inverse quantization hardware design. The results show that the design method in this paper could achieve the hardware block for the targeted FPGA platform efficiently and explore the design space of the hardware with different high level synthesis settings at the same time to fulfil the different requirements for different designs.
出处 《电子技术应用》 北大核心 2016年第11期25-28,共4页 Application of Electronic Technique
基金 福建省科技厅引导性项目(2015h0031)
关键词 H.264解码器 逆量化 逆变换 高层次综合 设计空间探索 H.264 decoder inverse quantification inverse transform high level synthesis design space exploration
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参考文献5

  • 1FLEMING K,LIN C C, DAVE N, et al.H.264 decoder:A case study in multiple design points[C].MEMOCODE.IEEE, 2008 : 165-174.
  • 2樊宗智,周煦林,刘彬.基于高层次综合的JPEG编码器设计[J].微电子学与计算机,2015,32(6):32-35. 被引量:5
  • 3WANG T C, HUANG Y W,FANG H C,et al.Parallel 4x4 2d transform and inverse transform architecture for mpeg-4 avc/h.264[C].ISCAS, vol.2.IEEE, 2003 : 11-800.
  • 4Zhong Guanwen, Vanchinathan Venkataramani, Yun Hang, et al.Design space exploration of multiple loops on FPGAs using high level synthesis[C].2014 32nd IIEEE International Conference on Computer Design, Seoul, South Korea, 2104 : 456 -463.
  • 5张茉莉,杨海钢,崔秀海,李园强.基于数组分块的FPGA高级综合编译优化算法[J].计算机应用研究,2013,30(11):3349-3352. 被引量:2

二级参考文献12

  • 1游余新.利用Mentor高层次综合技术(Catapult Synthesis)快速实现复杂DSP算法[J].中国集成电路,2007,16(5):35-41. 被引量:7
  • 2COUSSY P, GAJSKI D D, MEREDITH M, et al. An introduction to high-level synthesis[ J]. IEEE Design & Test of Computers ,2009,26(4) :8-17.
  • 3MARTIN G, SMITH G. High-level synthesis : past, present, and future [ J 1-IEEE Design & Test of Computers ,2009,26 (4):18-25.
  • 4CONG J, LIU B, NEUENDORFFER S,et al. High-level synthesis for FPGAs:from prototyping to deployment [ J ]. IEEE Trans on Com- puter-aided Design of Integrated Circuits and Systems,2011,30 (4) :473-491.
  • 5EDWARDS S A. The challenges of synthesizing hardware from C-Like languages[ J]. IEEE Design & Test of Computer, 2006,23 ( 5 ) : 375-386.
  • 6LI Peng, WANG Yu-xin, ZHANG Peng,et al. Memory partitioning and scheduling co-optimization in behavioral synthesis [ C ]//Proc of IEEE/ACM International Conference on Computer-Aided Design. 2012:488-495.
  • 7VlLLARREAL J, PARK A, NAJJAR W, et al. Designing modular hardware accelerators in C with ROCCC 2.0 [ C]//Proc of the Igth IEEE Annual International Symposium on Field-Programmable Custom Computing Machines. 2010 : 127-134.
  • 8CANIS A,CHOI J,GORT M,et al. LegUp 3.0[ CP/OL]. (2013-01- 21 ) [ 2013-02-20 ]. http ://legup. eecg. utoronto, ca.
  • 9ASHER Y B, ROTEM N. Automatic memory partitioning: increasing memory parallelism via data structure partitioning [ C ]//Proc of IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis( CODES + ISSS). 2010:155-160.
  • 10LLVM 3.0[ CP/OLI. (2013-01-21) [2013-02-20]. http://llvm. org/releases/.

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