基于FPGA的DDR3 SDRAM控制器的设计与优化

Design and Optimization of DDR3 SDRAM Controller Based on FPGA

为解决超高速采集系统中的数据缓存问题,文中基于Xilinx Kintex-7 FPGA MIG_v1.9 IP核进行了DDR3SDRAM控制器的编写,分析并提出了提高带宽利用率的方法。最终将其进行类FIFO接口的封装,屏蔽掉了DDR3 IP核复杂的用户接口,为DDR3数据流缓存的实现提供便利。系统测试表明,该设计满足大容量数据缓存要求,并具有较强的可移植性。

In order to solve the problem of data cache in ultrahigh speed sampling system, a DDR3 SDRAM controller is designed in this paper based on Kintex -7 FPGA MIG_v1. 9 IP core. A method to improve the bandwidth utilization ratio is proposed and analyzed. Finally, it is packaged as the FIFO interface, while shielding the complex user interface of DDR3 IP core, so that the DDR3 reading and writing operation can be as simple as FIFO＇s. System tests show that the proposed method meets the requirements of large capacity data cache, and provides with high portability.