应用于CMOS图像传感器的Pipelined SAR模数转换器设计

Design of a Pipelined SAR ADC Used in CMOS Image Sensor

设计实现一种应用于CMOS图像传感器的10bit模数转换器(ADC),采用基于逐次逼近的新型流水线结构(Pipelined SAR ADC).提出了一种优化选取其中高精度倍增数模转换器(MDAC)和单位电容值的解析方法.通过采用第一级高精度、半增益MDAC和动态比较器等技术提高了整体电路的线性度,并降低了系统功耗.通过对版图面积的优化设计,满足了CMOS图像传感器对芯片面积的要求.本设计基于180nm CMOS工艺,仿真结果显示电路实现了60.37dB的信噪失真比(SNDR)和76.37dB的无杂散动态范围(SFDR),有效精度(ENOB)达到了9.74bit.ADC的核心面积仅为140μmⅹ280μm,约为0.04mm2.在2.8V电压下,功耗为9.8mW.

This paper presents a novel architecture to achieve a 10 bit pipeline ADC based on SAR technique which is used in a CMOS image sensor. A theoretical analysis is proposed to determine the high resolution MDAC and the suitable value of unit capacitor. The high-resolution first stage, the half-gain MDAC and the dynamic comparator are adopted to improve the linearity and to reduce the power. To satisfy the strict area requirement of CMOS image sensor, the layout is carefully designed. This pipelined SAR ADC is designed and fabricated in SMIC 180 nm CMOS technology. Simulation results show the ADC achieves 60. 37 dB signal to noise distortion ratio （SNDR） and 76.37 dB spurious free dynamic range（SFDR）. The effective number of bits （ENOB） achieves 9. 74 bit. The core area is 140μm×280μm, about 0. 04 mm2. The power dissipation is 9. 8 mW in typical case under 2. 8 V supply.